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document no. e0827e10 (ver. 1.0) date published october 2005 (k) japan printed in japan url: http://www.elpida.com ? elpida memory, inc. 2005 data sheet 1gb ddr2 sdram so-dimm EBE11UD8AGSA (128m words 64 bits, 2 ranks) description the EBE11UD8AGSA is 128m words 64 bits, 2 ranks ddr2 sdram small outline dual in-line memory module, mounting 16 pieces of 512m bits ddr2 sdram sealed in fbga ( bga ? ) package. read and write operations are performed at the cross points of the ck and the /ck. this high-speed data transfer is realized by the 4 bits prefetch-pipelined architecture. data strobe (dqs and /dqs) both for read and write are available for high speed and reliable data bus design. by setting extended mode register, the on-chip delay locked loop (dll) can be set enable or disable. this module provides high density mounting without utilizing surface mount technology. decoupling capacitors are mounted beside each fbga ( bga) on the module board. note: do not push the components or drop the modules in order to avoid mechanical defects, which may result in electrical defects. features ? 200-pin socket type small outline dual in line memory module (so-dimm) ? pcb height: 30.0mm ? lead pitch: 0.6mm ? lead-free (rohs compliant) ? power supply: vdd = 1.8v 0.1v ? data rate: 667mbps /533mbps (max.) ? sstl_18 compatible i/o ? double-data-rate architecture: two data transfers per clock cycle ? bi-directional, differential data strobe (dqs and /dqs) is transmitted/received with data, to be used in capturing data at the receiver ? dqs is edge aligned with data for reads: center- aligned with data for writes ? differential clock inputs (ck and /ck) ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge: data and data mask referenced to both edges of dqs ? four internal banks for concurrent operation (components) ? data mask (dm) for write data ? burst lengths: 4, 8 ? /cas latency (cl): 3, 4, 5 ? auto precharge operation for each burst access ? auto refresh and self refresh modes ? average refresh period ? 7.8 s at 0 c tc + 85 c ? 3.9 s at + 85 c < tc + 95 c ? posted cas by programmable additive latency for better command and data bus efficiency ? off-chip-driver impedance ad justment and on-die- termination for better signal quality ? /dqs can be disabled for single-ended data strobe operation
EBE11UD8AGSA data sheet e0827e10 (ver. 1.0) 2 ordering information part number data rate mbps (max.) component jedec speed bin (cl-trcd-trp) package contact pad mounted devices EBE11UD8AGSA-6e-e 667 ddr2-667 (5-5-5) 200-pin so-dimm (lead-free) gold ede5108agse-6e-e EBE11UD8AGSA-5c-e 533 ddr2-533 (4-4-4) ede5108agse-6e-e ede5108agse-5c-e pin configurations 1 pin 2 pin front side back side 39 pin 40 pin 41 pin 42 pin 199 pin 200 pin front side back side pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 vref 51 dqs2 2 vss 52 dm2 3 vss 53 vss 4 dq4 54 vss 5 dq0 55 dq18 6 dq5 56 dq22 7 dq1 57 dq19 8 vss 58 dq23 9 vss 59 vss 10 dm0 60 vss 11 /dqs0 61 dq24 12 vss 62 dq28 13 dqs0 63 dq25 14 dq6 64 dq29 15 vss 65 vss 16 dq7 66 vss 17 dq2 67 dm3 18 vss 68 /dqs3 19 dq3 69 nc 20 dq12 70 dqs3 21 vss 71 vss 22 dq13 72 vss 23 dq8 73 dq26 24 vss 74 dq30 25 dq9 75 dq27 26 dm1 76 dq31 27 vss 77 vss 28 vss 78 vss 29 /dqs1 79 cke0 30 ck0 80 cke1 31 dqs1 81 vdd 32 /ck0 82 vdd 33 vss 83 nc 34 vss 84 nc 35 dq10 85 nc 36 dq14 86 nc 37 dq11 87 vdd 38 dq15 88 vdd 39 vss 89 a12 40 vss 90 a11 41 vss 91 a9 42 vss 92 a7 43 dq16 93 a8 44 dq20 94 a6 45 dq17 95 vdd 46 dq21 96 vdd 47 vss 97 a5 48 vss 98 a4 49 /dqs2 99 a3 50 nc 100 a2
EBE11UD8AGSA data sheet e0827e10 (ver. 1.0) 3 front side back side pin no. pin name pin no. pin name pin no. pin name pin no. pin name 101 a1 151 dq42 102 a0 152 dq46 103 vdd 153 dq43 104 vdd 154 dq47 105 a10/ap 155 vss 106 ba1 156 vss 107 ba0 157 dq48 108 /ras 158 dq52 109 /we 159 dq49 110 /cs0 160 dq53 111 vdd 161 vss 112 vdd 162 vss 113 /cas 163 nc 114 odt0 164 ck1 115 /cs1 165 vss 116 a13 166 /ck1 117 vdd 167 /dqs6 118 vdd 168 vss 119 odt1 169 dqs6 120 nc 170 dm6 121 vss 171 vss 122 vss 172 vss 123 dq32 173 dq50 124 dq36 174 dq54 125 dq33 175 dq51 126 dq37 176 dq55 127 vss 177 vss 128 vss 178 vss 129 /dqs4 179 dq56 130 dm4 180 dq60 131 dqs4 181 dq57 132 vss 182 dq61 133 vss 183 vss 134 dq38 184 vss 135 dq34 185 dm7 136 dq39 186 /dqs7 137 dq35 187 vss 138 vss 188 dqs7 139 vss 189 dq58 140 dq44 190 vss 141 dq40 191 dq59 142 dq45 192 dq62 143 dq41 193 vss 144 vss 194 dq63 145 vss 195 sda 146 /dqs5 196 vss 147 dm5 197 scl 148 dqs5 198 sa0 149 vss 199 vddspd 150 vss 200 sa1
EBE11UD8AGSA data sheet e0827e10 (ver. 1.0) 4 pin description pin name function a0 to a13 address input row address a0 to a13 column address a0 to a9 a10 (ap) auto precharge ba0, ba1 bank select address dq0 to dq63 data input/output /ras row address strobe command /cas column address strobe command /we write enable /cs0, /cs1 chip select cke0, cke1 clock enable ck0, ck1 clock input /ck0, /ck1 differential clock input dqs0 to dqs7, /dqs0 to /dqs7 input and output data strobe dm0 to dm7 input mask scl clock input for serial pd sda data input/output for serial pd sa0, sa1 serial address input vdd power for internal circuit vddspd power for serial eeprom vref input reference voltage vss ground odt0, odt1 odt control nc no connection
EBE11UD8AGSA data sheet e0827e10 (ver. 1.0) 5 serial pd matrix byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 0 number of bytes utilized by module manufacturer 1 0 0 0 0 0 0 0 80h 128 bytes 1 total number of bytes in serial pd device 0 0 0 0 1 0 0 0 08h 256 bytes 2 memory type 0 0 0 0 1 0 0 0 08h ddr2 sdram 3 number of row address 0 0 0 0 1 1 1 0 0eh 14 4 number of column address 0 0 0 0 1 0 1 0 0ah 10 5 number of dimm ranks 0 1 1 0 0 0 0 1 61h 2 6 module data width 0 1 0 0 0 0 0 0 40h 64 7 module data width continuation 0 0 0 0 0 0 0 0 00h 0 8 voltage interface level of this assembly 0 0 0 0 0 1 0 1 05h sstl 1.8v 9 ddr sdram cycle time, cl = 5 -6e 0 0 1 1 0 0 0 0 30h 3.0ns* 1 -5c 0 0 1 1 1 1 0 1 3dh 3.75ns* 1 10 sdram access from clock (tac) -6e 0 1 0 0 0 1 0 1 45h 0.45ns* 1 -5c 0 1 0 1 0 0 0 0 50h 0.5ns* 1 11 dimm configuration type 0 0 0 0 0 0 0 0 00h none. 12 refresh rate/type 1 0 0 0 0 0 1 0 82h 7.8 s 13 primary sdram width 0 0 0 0 1 0 0 0 08h 8 14 error checking sdram width 0 0 0 0 0 0 0 0 00h none. 15 reserved 0 0 0 0 0 0 0 0 00h 0 16 sdram device attributes: burst length supported 0 0 0 0 1 1 0 0 0ch 4,8 17 sdram device attributes: number of banks on sdram device 0 0 0 0 0 1 0 0 04h 4 18 sdram device attributes: /cas latency 0 0 1 1 1 0 0 0 38h 3, 4, 5 19 dimm mechanical characteristics 0 0 0 0 0 0 0 1 01h 3.80mm max. 20 dimm type information 0 0 0 0 0 1 0 0 04h so-dimm 21 sdram module attributes 0 0 0 0 0 0 0 0 00h normal 22 sdram device attributes: general 0 0 0 0 0 0 1 1 03h weak driver 50 ? odt support 23 minimum clock cycle time at cl = 4 0 0 1 1 1 1 0 1 3dh 3.75ns* 1 24 maximum data access time (tac) from clock at cl = 4 0 1 0 1 0 0 0 0 50h 0.5ns* 1 25 minimum clock cycle time at cl = 3 0 1 0 1 0 0 0 0 50h 5.0ns* 1 26 maximum data access time (tac) from clock at cl = 3 0 1 1 0 0 0 0 0 60h 0.6ns* 1 27 minimum row precharge time (trp) 0 0 1 1 1 1 0 0 3ch 15ns 28 minimum row active to row active delay (trrd) 0 0 0 1 1 1 1 0 1eh 7.5ns 29 minimum /ras to /cas delay (trcd) 0 0 1 1 1 1 0 0 3ch 15ns 30 minimum active to precharge time (tras) 0 0 1 0 1 1 0 1 2dh 45ns 31 module rank density 1 0 0 0 0 0 0 0 80h 512m bytes
EBE11UD8AGSA data sheet e0827e10 (ver. 1.0) 6 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 32 address and command setup time before clock (tis) -6e 0 0 1 0 0 0 0 0 20h 0.20ns* 1 -5c 0 0 1 0 0 1 0 1 25h 0.25ns* 1 33 address and command hold time after clock (tih) -6e 0 0 1 0 1 0 0 0 28h 0.28ns* 1 -5c 0 0 1 1 1 0 0 0 38h 0.38ns* 1 34 data input setup time before clock (tds) 0 0 0 1 0 0 0 0 10h 0.10ns* 1 35 data input hold time after clock (tdh) -6e 0 0 0 1 1 0 0 0 18h 0.18ns* 1 -5c 0 0 1 0 0 0 1 1 23h 0.23ns* 1 36 write recovery time (twr) 0 0 1 1 1 1 0 0 3ch 15ns* 1 37 internal write to read command delay (twtr) 0 0 0 1 1 1 1 0 1eh 7.5ns* 1 38 internal read to precharge command delay (trtp) 0 0 0 1 1 1 1 0 1eh 7.5ns* 1 39 memory analysis probe characteristics 0 0 0 0 0 0 0 0 00h tbd 40 extension of byte 41 and 42 0 0 0 0 0 0 0 0 00h undefined 41 active command period (trc) 0 0 1 1 1 1 0 0 3ch 60ns* 1 42 auto refresh to active/ auto refresh command cycle (trfc) 0 1 1 0 1 0 0 1 69h 105ns* 1 43 sdram tck cycle max. (tck max.) 1 0 0 0 0 0 0 0 80h 8ns* 1 44 dout to dqs skew -6e 0 0 0 1 1 0 0 0 18h 0.24ns* 1 -5c 0 0 0 1 1 1 1 0 1eh 0.30ns* 1 45 data hold skew (tqhs) -6e 0 0 1 0 0 0 1 0 22h 0.34ns* 1 -5c 0 0 1 0 1 0 0 0 28h 0.40ns* 1 46 pll relock time 0 0 0 0 0 0 0 0 00h undefined 47 to 61 0 0 0 0 0 0 0 0 00h 62 spd revision 0 0 0 1 0 0 1 0 12h rev. 1.2 63 checksum for bytes 0 to 62 -6e 0 1 1 1 0 1 1 0 76h -5c 1 0 1 1 1 0 1 0 bah 64 to 65 manufacturer?s jedec id code 0 1 1 1 1 1 1 1 7fh continuation code 66 manufacturer?s jedec id code 1 1 1 1 1 1 1 0 feh elpida memory 67 to 71 manufacturer?s jedec id code 0 0 0 0 0 0 0 0 00h 72 manufacturing location (ascii-8bit code) 73 module part number 0 1 0 0 0 1 0 1 45h e 74 module part number 0 1 0 0 0 0 1 0 42h b 75 module part number 0 1 0 0 0 1 0 1 45h e 76 module part number 0 0 1 1 0 0 0 1 31h 1 77 module part number 0 0 1 1 0 0 0 1 31h 1 78 module part number 0 1 0 1 0 1 0 1 55h u 79 module part number 0 1 0 0 0 1 0 0 44h d 80 module part number 0 0 1 1 1 0 0 0 38h 8
EBE11UD8AGSA data sheet e0827e10 (ver. 1.0) 7 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 81 module part number 0 1 0 0 0 0 0 1 41h a 82 module part number 0 1 0 0 0 1 1 1 47h g 83 module part number 0 1 0 1 0 0 1 1 53h s 84 module part number 0 1 0 0 0 0 0 1 41h a 85 module part number 0 0 1 0 1 1 0 1 2dh ? 86 module part number -6e 0 0 1 1 0 1 1 0 36h 6 -5c 0 0 1 1 0 1 0 1 35h 5 87 module part number -6e 0 1 0 0 0 1 0 1 45h e -5c 0 1 0 0 0 0 1 1 43h c 88 module part number 0 0 1 0 1 1 0 1 2dh ? 89 module part number 0 1 0 0 0 1 0 1 45h e 90 module part number 0 0 1 0 0 0 0 0 20h (space) 91 revision code 0 0 1 1 0 0 0 0 30h initial 92 revision code 0 0 1 0 0 0 0 0 20h (space) 93 manufacturing date year code (bcd) 94 manufacturing date week code (bcd) 95 to 98 module serial number 99 to 127 manufacture specific data note: 1. these specifications are defined based on component sp ecification, not module.
EBE11UD8AGSA data sheet e0827e10 (ver. 1.0) 8 block diagram r s1 dm3 dqs3 r s1 dm0 ba0 to ba1: sdrams (d0 to d15) a0 to a13: sdrams (d0 to d15) ba0 to ba1 /ras: sdrams (d0 to d15) vddspd spd vref sdrams (d0 to d15) vdd sdrams (d0 to d15, vdd and vddq) vss sdrams (d0 to d15, spd) /dqs0 dq0 to dq7 8 /ras /cas /we a0 to a13 /cas: sdrams (d0 to d15) /we: sdrams (d0 to d15) /cs0 /cs1 d5 d4 r s1 r s1 r s1 r s1 dm4 /dqs4 dqs0 r s1 r s1 dqs4 r s1 r s1 dq8 to dq15 8 r s1 8 r s1 dq40 to dq47 8 r s1 dq16 to dq23 8 d3 d6 r s1 dq24 to dq31 8 r s1 dm5 dqs5 r s1 /dqs5 r s1 r s1 dm6 dqs6 r s1 r s1 dm7 dqs7 r s1 /dqs3 r s1 /dqs7 r s1 dm1 dqs1 r s1 /dqs1 r s1 r s1 dm2 dqs2 r s1 r s1 /dqs6 r s1 /dqs2 r s1 r s3 r s3 r s3 r s3 r s3 dq48 to dq55 8 r s1 dq56 to dq63 8 r s1 d2 * d0 to d15 : 512m bits ddr2 sdram u0 : 2k bits eeprom rs1 : 22 ? rs2 : 3.0 ? rs3 : 10.0 ? dq0 to dq7 dq0 to dq7 dq0 to dq7 odt1 cke1 dq0 to dq7 dq0 to dq7 d0 /cs odt dq0 to dq7 /dqs d13 d12 d14 dq0 to dq7 dq0 to dq7 dq0 to dq7 d7 dq0 to dq7 d15 dq0 to dq7 dq32 to dq39 d11 dq0 to dq7 odt0 cke0 r s2 r s2 r s2 r s2 r s2 r s2 d8 dq0 to dq7 dqs dm cke d1 dq0 to dq7 /cs odt /dqs dqs dm cke /cs odt /dqs dqs dm cke /cs odt /dqs dqs dm cke /cs odt /dqs dqs dm cke /cs odt /dqs dqs dm cke /cs odt /dqs dqs dm cke /cs odt /dqs dqs dm cke /cs odt /dqs dqs dm cke /cs odt /dqs dqs dm cke /cs odt /dqs dqs dm cke /cs odt /dqs dqs dm cke /cs odt /dqs dqs dm cke /cs odt /dqs dqs dm cke d9 dq0 to dq7 /cs odt /dqs dqs dm cke /cs odt /dqs dqs dm cke d10 dq0 to dq7 serial pd sda a0 a1 a2 wp scl sa0 sa1 sda scl notes : 1. dq wiring may be changed within a byte. 2. dq, dqs, /dqs, odt, dm, cke, /cs relationships must be meintained as shown. u0 8 loads ck0 /ck0 8 loads ck1 /ck1 6.0pf 6.0pf
EBE11UD8AGSA data sheet e0827e10 (ver. 1.0) 9 electrical specifications ? all voltages are referenced to vss (gnd). absolute maximum ratings parameter symbol value unit note voltage on any pin relative to vss vt ?0.5 to +2.3 v 1 supply voltage relative to vss vdd ?0.5 to +2.3 v short circuit output current ios 50 ma 1 power dissipation pd 8 w operating case temperature tc 0 to +95 c 1, 2 storage temperature tstg ?55 to +100 c 1 note: 1. ddr2 sdram component specification. 2. supporting 0 c to +85c and being able to extend to +95c with doubling auto-refresh commands in frequency to a 32ms period (trefi = 3.9 s) and higher temperature self-refresh entry via the control of emrs (2) bit a7 is required. caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this sp ecification exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc operating conditions (tc = 0c to +85 c) (ddr2 sdram component specification) parameter symbol min. typ. max. unit notes supply voltage vdd, vddq 1.7 1.8 1.9 v 4 vss 0 0 0 v vddspd 1.7 ? 3.6 v input reference voltage vref 0.49 vddq 0.50 vddq 0.51 vddq v 1, 2 termination voltage vtt vref ? 0.04 vref vref + 0.04 v 3 dc input logic high vih (dc) vref + 0.125 ? vddq + 0.3v v dc input low vil (dc) ? 0.3 ? vref ? 0.125 v ac input logic high -6e vih (ac) vref + 0.200 ? ? v -5c vih (ac) vref + 0.250 ? ? v ac input low -6e vil (ac) ? ? vref ? 0.200 v -5c vil (ac) ? ? vref ? 0.250 v notes: 1. the value of vref may be selected by the user to provide optimum noise margin in the system. typically the value of vref is expected to be about 0.5 vddq of the transmitting device and vref are expected to track variations in vddq. 2. peak to peak ac noise on vref may not exceed 2% vref (dc). 3. vtt of transmitting device must track vref of receiving device. 4. vddq must be equal to vdd.
EBE11UD8AGSA data sheet e0827e10 (ver. 1.0) 10 dc characteristics 1 (tc = 0c to +85 c, vdd = 1.8v 0.1v) parameter symbol grade max. unit test condition operating current (act-pre) (another rank is in idd2p) idd0 -6e -5c 1000 960 ma operating current (act-pre) (another rank is in idd3n) idd0 -6e -5c 1480 1400 ma one bank; tck = tck (idd), trc = trc (idd), tras = tras min.(idd); cke is h, /cs is h between valid commands; address bus inputs are switching; data bus inputs are switching operating current (act-read-pre) (another rank is in idd2p) idd1 -6e -5c 1120 1080 ma operating current (act-read-pre) (another rank is in idd3n) idd1 -6e -5c 1600 1520 ma one bank; iout = 0ma; bl = 4, cl = cl(idd), al = 0; tck = tck (idd), trc = trc (idd), tras = tras min.(idd); trcd = trcd (idd); cke is h, /cs is h between valid commands; address bus inputs are switching; data pattern is same as idd4w precharge power-down standby current idd2p 160 ma all banks idle; tck = tck (idd); cke is l; other control and address bus inputs are stable; data bus inputs are floating precharge quiet standby current idd2q 400 ma all banks idle; tck = tck (idd); cke is h, /cs is h; other control and address bus inputs are stable; data bus inputs are floating idle standby current idd2n -6e -5c 560 480 ma all banks idle; tck = tck (idd); cke is h, /cs is h; other control and address bus inputs are switching; data bus inputs are switching idd3p-f 640 ma fast pdn exit mrs(12) = 0 active power-down standby current idd3p-s 400 ma all banks open; tck = tck (idd); cke is l; other control and address bus inputs are stable; data bus inputs are floating slow pdn exit mrs(12) = 1 active standby current idd3n -6e -5c 1120 1040 ma all banks open; tck = tck (idd), tras = tras max.(idd), trp = trp (idd); cke is h, /cs is h between valid commands; other control and address bus inputs are switching; data bus inputs are switching operating current (burst read operating) (another rank is in idd2p) idd4r -6e -5c 1920 1600 ma operating current (burst read operating) (another rank is in idd3n) idd4r -6e -5c 2400 2040 ma all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; tck = tck (idd), tras = tras max.(idd), trp = trp (idd); cke is h, /cs is h between valid commands; address bus inputs are switching; data pattern is same as idd4w operating current (burst write operating) (another rank is in idd2p) idd4w -6e -5c 1840 1600 ma operating current (burst write operating) (another rank is in idd3n) idd4w -6e -5c 2320 2040 ma all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; tck = tck (idd), tras = tras max.(idd), trp = trp (idd); cke is h, /cs is h between valid commands; address bus inputs are switching; data bus inputs are switching
EBE11UD8AGSA data sheet e0827e10 (ver. 1.0) 11 parameter symbol grade max. unit test condition auto-refresh current (another rank is in idd2p) idd5 -6e -5c 2240 2080 ma auto-refresh current (another rank is in idd3n) idd5 -6e -5c 2720 2520 ma tck = tck (idd); refresh command at every trfc (idd) interval; cke is h, /cs is h between valid commands; other control and address bus inputs are switching; data bus inputs are switching self-refresh current idd6 96 ma self refresh mode; ck and /ck at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating operating current (bank interleaving) (another rank is in idd2p) idd7 2640 ma operating current (bank interleaving) (another rank is in idd3n) idd7 -6e -5c 3120 3080 ma all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = trcd (idd) ? 1 tck (idd); tck = tck (idd), trc = trc (idd), trrd = trrd(idd), trcd = 1 tck (idd); cke is h, cs is h between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4w; notes: 1. idd specificati ons are tested after the device is properly initialized. 2. input slew rate is specifie d by ac input test condition. 3. idd parameters are spec ified with odt disabled. 4. data bus consists of dq, dm, dqs, /dqs, rdqs, /rdqs, ldqs , /ldqs, udqs, and /udqs. idd values must be met with all combinations of emrs bits 10 and 11. 5. definitions for idd l is defined as vin vil (ac) (max.) h is defined as vin vih (ac) (min.) stable is defined as inputs stable at an h or l level floating is defined as inputs at vref = vddq/2 switching is defined as: inputs changing between h and l every other clock cycle (once per two clocks) for address and control signals, and inputs changing between h and l every othe r data transfer (once per clock) for dq signals not including masks or strobes. 6. refer to ac timing for idd test conditions. ac timing for idd test conditions for purposes of idd testing, the foll owing parameters are to be utilized. ddr2-667 ddr2-533 parameter 5-5-5 4-4-4 unit cl(idd) 5 4 tck trcd(idd) 15 15 ns trc(idd) 60 60 ns trrd(idd) 7.5 7.5 ns tck(idd) 3 3.75 ns tras(min.)(idd) 45 45 ns tras(max.)(idd) 70000 70000 ns trp(idd) 15 15 ns trfc(idd) 105 105 ns
EBE11UD8AGSA data sheet e0827e10 (ver. 1.0) 12 dc characteristics 2 (tc = 0c to +85 c, vdd, vddq = 1.8v 0.1v) (ddr2 sdram component specification) parameter symbol value unit notes input leakage current ? ili ? 2 a vdd vin vss output leakage current ? ilo ? 5 a vddq vout vss minimum required output pull-up under ac test load voh vtt + 0.603 v 5 maximum required output pull-down under ac test load vol vtt ? 0.603 v 5 output timing measurement reference level votr 0.5 vddq v 1 output minimum sink dc current iol +13.4 ma 3, 4, 5 output minimum source dc current ioh ? 13.4 ma 2, 4, 5 notes: 1. the vddq of the dev ice under test is referenced. 2. vddq = 1.7v; vout = 1.42v. 3. vddq = 1.7v; vout = 0.28v. 4. the dc value of vref applied to the receiving device is expected to be set to vtt. 5. after ocd calibration to 18 ? at tc = 25 c, vdd = vddq = 1.8v. dc characteristics 3 (tc = 0c to +85 c, vdd, vddq = 1.8v 0.1v) (ddr2 sdram component specification) parameter symbol min. max. unit notes ac differential input voltage vid (ac) 0.5 vddq + 0.6 v 1, 2 ac differential cross point voltage vix (ac) 0.5 vddq ? 0.175 0.5 vddq + 0.175 v 2 ac differential cross point voltage vox (ac) 0.5 vddq ? 0.125 0.5 vddq + 0.125 v 3 notes: 1. vid(ac) specifies the input differential voltage |vtr -vcp| required for switching, where vtr is the true input signal (such as ck, dqs, ldqs or udqs) and vcp is the complementary input signal (such as /ck, /dqs, /ldqs or /udqs). the minimum value is equal to vih(ac) ? vil(ac). 2. the typical value of vix(ac ) is expected to be about 0.5 vddq of the transmitting device and vix(ac) is expected to track variations in vddq . vix(ac) i ndicates the voltage at which differential input signals must cross. 3. the typical value of vox(ac) is expected to be about 0.5 vddq of the transmitting device and vox(ac) is expected to track variations in vddq . vox(ac) indicates the voltage at which differential output signals must cross. crossing point vssq vtr vcp vid vix or vox vddq differential signal levels*1, 2
EBE11UD8AGSA data sheet e0827e10 (ver. 1.0) 13 odt dc electrical characteristics (tc = 0c to +85 c, vdd, vddq = 1.8v 0.1v) (ddr2 sdram component specification) parameter symbol min. typ. max. unit note rtt effective impedance value for emrs (a6, a2) = 0, 1 ; 75 ? rtt1(eff) 60 75 90 ? 1 rtt effective impedance value for emrs (a6, a2) = 1, 0 ; 150 ? rtt2(eff) 120 150 180 ? 1 rtt effective impedance value for emrs (a6, a2) = 1, 1 ; 50 ? rtt3(eff) 40 50 60 ? 1 deviation of vm with respect to vddq/2 ? vm ? 6 ? + 6 % 1 note: 1. test condition for rtt measurements. measurement definition for rtt(eff) apply vih (ac) and vil (ac) to test pin separately, th en measure current i(vih(ac)) and i(vil(ac)) respectively. vih(ac), and vddq values defined in sstl _ 18. vih(ac) ? vil(ac) i(vih(ac)) ? i(vil(ac)) rtt(eff) = measurement definition for vm measure voltage (vm) at test pin (midpoint) with no load. 2 vm vddq ? vm = 100% ? 1 ocd default characteristics (tc = 0c to +85 c, vdd, vddq = 1.8v 0.1v) (ddr2 sdram component specification) parameter min typ max unit notes output impedance 12.6 18 23.4 ? 1 pull-up and pull-down mismatch 0 ? 4 ? 1, 2 output slew rate 1.5 ? 5 v/ns 3, 4 notes: 1. impedance measurement condition for output source dc current: vddq = 1.7v; vout = 1420mv; (vout ? vddq)/ioh must be less than 23.4 ? for values of vout between vddq and vddq ? 280mv. impedance measurement condition for output si nk dc current: vddq = 1.7v; vout = 280mv; vout/iol must be less than 23.4 ? for values of vout between 0v and 280mv. 2. mismatch is absolute value between pull up and pull down, both are measured at same temperature and voltage. 3. slew rate measured from vil(ac) to vih(ac). 4. the absolute value of the slew rate as measured from dc to dc is equal to or greater than the slew rate as measured from ac to ac. this is guaranteed by design and characterization.
EBE11UD8AGSA data sheet e0827e10 (ver. 1.0) 14 pin capacitance (ta = 25c, vdd = 1.8v 0.1v) (ddr2 sdram component specification) parameter symbol pins min. max. unit note input capacitance ci1 address, /ras, /cas, /we, /cs, cke, odt 1.0 2.0 pf 1 input capacitance ci2 ck, /ck 1.0 2.0 pf 1 input/output pin capacitance -6e ci/o 2.5 3.5 pf 2 -5c dq, dqs, /dqs, rdqs, /rdqs, dm 2.5 4.0 pf 2 notes: 1. matching within 0.25pf. 2. matching within 0.50pf.
EBE11UD8AGSA data sheet e0827e10 (ver. 1.0) 15 ac characteristics (tc = 0c to +85 c, vdd, vddq = 1.8v 0.1v, vss = 0v) (ddr2 sdram component specification) -6e -5c frequency (mbps) 667 533 parameter symbol min. max. min. max. unit notes /cas latency cl 5 5 4 5 tck active to read or write command delay trcd 15 ? 15 ? ns precharge command period trp 15 ? 15 ? ns active to active/auto refresh command time trc 60 ? 60 ? ns dq output access time from ck, /ck tac ? 450 +450 ? 500 +500 ps dqs output access time from ck, /ck tdqsck ? 400 +400 ? 450 +450 ps ck high-level width tch 0.45 0.55 0.45 0.55 tck ck low-level width tcl 0.45 0.55 0.45 0.55 tck ck half period thp min. (tcl, tch) ? min. (tcl, tch) ? ps clock cycle time tck 3000 8000 3750 8000 ps dq and dm input hold time tdh 175 ? 225 ? ps 5 dq and dm input setup time tds 100 ? 100 ? ps 4 control and address input pulse width for each input tipw 0.6 ? 0.6 ? tck dq and dm input pulse width for each input tdipw 0.35 ? 0.35 ? tck data-out high-impedance time from ck,/ck thz ? tac max. ? tac max. ps data-out low-impedance time from ck,/ck tlz ta c min. tac max. tac min. tac max. ps dqs-dq skew for dqs and associated dq signals tdqsq ? 240 ? 300 ps dq hold skew factor tqhs ? 340 ? 400 ps dq/dqs output hold time from dqs tqh thp ? tqhs ? thp ? tqhs ? ps write command to first dqs latching transition tdqss wl ? 0.25 wl + 0.25 wl ? 0.25 wl + 0.25 tck dqs input high pulse width tdqsh 0.35 ? 0.35 ? tck dqs input low pulse width tdqsl 0.35 ? 0.35 ? tck dqs falling edge to ck setup time tdss 0.2 ? 0.2 ? tck dqs falling edge hold time from ck tdsh 0.2 ? 0.2 ? tck mode register set command cycle time tmrd 2 ? 2 ? tck write postamble twpst 0.4 0.6 0.4 0.6 tck write preamble twpre 0.35 ? 0.35 ? tck address and control input hold time tih 275 ? 375 ? ps 5 address and control input setup time tis 200 ? 250 ? ps 4 read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck active to precharge command tras 45 70000 45 70000 ns active to auto-precharge delay trap trcd min. ? trcd min. ? ns active bank a to active bank b command period trrd 7.5 ? 7.5 ? ns write recovery time twr 15 ? 15 ? ns auto precharge write recovery + precharge time tdal (twr/tck)+ (trp/tck) ? (twr/tck)+ (trp/tck) ? tck 1
EBE11UD8AGSA data sheet e0827e10 (ver. 1.0) 16 -6e -5c frequency (mbps) 667 533 parameter symbol min. max. min. max. unit notes internal write to read command delay twtr 7.5 ? 7.5 ? ns internal read to precharge command delay trtp 7.5 ? 7.5 ? ns exit self refresh to a non-read command txsnr trfc + 10 ? trfc + 10 ? ns exit self refresh to a read command txsrd 200 ? 200 ? tck exit precharge power down to any non-read command txp 2 ? 2 ? tck exit active power down to read command txard 2 ? 2 ? tck 3 exit active power down to read command (slow exit/low power mode) txards 7 ? al ? 6 ? al ? tck 2, 3 cke minimum pulse width (high and low pulse width) tcke 3 ? 3 ? tck output impedance test driver delay toit 0 12 0 12 ns auto refresh to active/auto refresh command time trfc 105 ? 105 ? ns average periodic refresh interval (0 c tc +85 c) trefi ? 7.8 ? 7.8 s (+85 c < tc +95 c) trefi ? 3.9 ? 3.9 s minimum time clocks remains on after cke asynchronously drops low tdelay tis + tck + tih ? tis + tck + tih ? ns notes: 1. for each of the terms above, if not alr eady an integer, round to the next higher integer. 2. al: additive latency. 3. mrs a12 bit defines which active power down exit timing to be applied. 4. the figures of input waveform timing 1 and 2 are referenced from the input signal crossing at the vih(ac) level for a rising signal and vil(ac) for a falling signal applied to the device under test. 5. the figures of input waveform timing 1 and 2 are referenced from the input signal crossing at the vih(dc) level for a rising signal and vil(dc) for a falling signal applied to the device under test. dqs /dqs tds tdh tds tdh vddq vih (ac)(min.) vih (dc)(min.) vil (dc)(max.) vil (ac)(max.) vss vref ck /ck tis tih tis tih vddq vih (ac)(min.) vih (dc)(min.) vil (dc)(max.) vil (ac)(max.) vss vref input waveform timing 1 (tds, tdh) input waveform timing 2 (tis, tih)
EBE11UD8AGSA data sheet e0827e10 (ver. 1.0) 17 odt ac electrical characteristics (ddr2 sdram component specification) parameter symbol min max unit notes odt turn-on delay taond 2 2 tck odt turn-on -6e taon tac(min) tac(max) + 700 ps 1 -5c taon tac(min) tac(max) + 1000 ps 1 odt turn-on (power down mode) taonpd tac(min) + 2000 2tck + tac(max) + 1000 ps odt turn-off delay taofd 2.5 2.5 tck odt turn-off taof tac(min) tac(max) + 600 ps 2 odt turn-off (power down mode) taofpd tac(min) + 2000 2.5tck + tac(max) + 1000 ps odt to power down entry latency tanpd 3 3 tck odt power down exit latency taxpd 8 8 tck notes: 1. odt turn on time min is when the device le aves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measured from taond. 2. odt turn off time min is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from taofd. ac input test conditions parameter symbol value unit notes input reference voltage vref 0.5 vddq v 1 input signal maximum peak to peak swing vswing(max.) 1.0 v 1 input signal maximum slew rate slew 1.0 v/ns 2, 3 notes: 1. input waveform timing is referenced to the inpu t signal crossing through the vref level applied to the device under test. 2. the input signal minimum slew rate is to be ma intained over the range from vil(dc) (max.) to vih(ac) (min.) for rising edges and the range from vih(dc) (min. ) to vil(ac) (max.) for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switching from vil(ac) to vih(ac) on the positive transitions and vih(ac) to vil( ac) on the negative transitions. vswing(max.) ? tr ? tf start of falling edge input timing start of rising edge input timing vih (dc) (min.) ? vil (ac) (max.) ? tf falling slew = vddq vih (ac)(min.) vih (dc)(min.) vil (dc)(max.) vil (ac)(max.) vss vref vih (ac) min. ? vil (dc) (max.) ? tr rising slew = ac input test signal wave forms vtt measurement point dq rt =25 ? output load
EBE11UD8AGSA data sheet e0827e10 (ver. 1.0) 18 pin functions ck, /ck (input pin) the ck and the /ck are the master clock inputs. all in puts except dms, dqss and dqs are referred to the cross point of the ck rising edge and the vref level. when a read operation, dqss and dqs are referred to the cross point of the ck and the /ck. when a write operation, dms and dqs are referr ed to the cross point of the dqs and the vref level. dqss for write operation are refe rred to the cross point of the ck and the /ck. /cs (input pin) when /cs is low, commands and data can be input. when /cs is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. /ras, /cas, and /we (input pins) these pins define operating commands (re ad, write, etc.) depending on the comb inations of their voltage levels. see "command operation". a0 to a13 (input pins) row address (ax0 to ax13) is determined by the a0 to the a13 level at the cross point of the ck rising edge and the vref level in a bank active command cycle. column addre ss (ay0 to ay9) is loaded via the a0 to the a9 at the cross point of the ck rising edge and the vref level in a read or a write command cycle. this column address becomes the starting addre ss of a burst operation. a10 (ap) (input pin) a10 defines the precharge mode when a precharge command, a read command or a write command is issued. if a10 = high when a precharge command is issued, all banks are precharged. if a10 = low when a precharge command is issued, only the bank that is selected by ba 1, ba0 is precharged. if a10 = high when read or write command, auto-precharge function is enabled. while a10 = low, auto-precharge function is disabled. ba0 and ba1 (input pins) ba0, ba1 are bank select signals (ba). the memory array is divided into bank 0, bank 1, bank 2 and bank 3. (see bank select signal table) [bank select signal table] ba0 ba1 bank 0 l l bank 1 h l bank 2 l h bank 3 h h remark: h: vih. l: vil. cke (input pin) cke controls power down and self-refresh. the powe r down and the self-refresh commands are entered when the cke is driven low and exited when it resumes to high. the cke level must be kept for 1 ck cycle at least, that is , if cke changes at the cross point of the ck rising edge and the vref level with proper setup time tis, at the next ck rising edge cke level must be kept with proper hold time tih. dq (input and output pins) data are input to and output from these pins. dqs and /dqs (input and output pin) dqs and /dqs provide the read data strobes (as output) and the write data strobes (as input).
EBE11UD8AGSA data sheet e0827e10 (ver. 1.0) 19 dm (input pins) dm is the reference signal of the dat a input mask function. dms are sampl ed at the cross point of dqs and /dqs. vdd (power supply pins) 1.8v is applied. (vdd is for the internal circuit.) vddspd (power supply pin) 1.8v is applied (for serial eeprom). vss (power supply pin) ground is connected. detailed operation part and timing waveforms refer to the ede5104agse, ed e5108agse datasheet (e0715e).
EBE11UD8AGSA data sheet e0827e10 (ver. 1.0) 20 physical outline 67.60 17.55 11.55 2.15 47.40 2.45 2.15 2.45 11.40 30.00 1 2 unit: mm 1.00 0.10 4.00 min 4.00 3.80 max (datum -a-) 4x full r component area (back) eca-ts2-0106-01 b a c 4.20 2.70 detail b detail a 0.51 max 0.25 max 0.51 max 2.55 min 4.00 0.10 0.60 0.45 0.03 1.00 0.10 detail c full r 4.20 2.40 detail d front side back side 20.00 d contact pad 6.00 63.60 2.00 min 200 199 (datum -a-) component area (front)
EBE11UD8AGSA data sheet e0827e10 (ver. 1.0) 21 caution for handling memory modules when handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ics, chip capacitors and chip resistors. it is necessary to avoid undue mechanical stress on these components to prevent damaging them. in particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. when re-packing memory modules, be sure the modules are not touching each other. modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. mde0202 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
EBE11UD8AGSA data sheet e0827e10 (ver. 1.0) 22 bga is a registered trademark of tessera, inc. all other trademarks are the intellectual property of their respective owners. m01e0107 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] this product is not designed to be resistant to electromagnetic waves or radiation. this product must be used in a non-condensing environment. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

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